This invention relates to manufacturing of integrated circuit devices. More particularly, this invention relates to a process for interconnecting multiple devices (generally with different sizes, architectures and functions) at close proximity and with a very high wiring density.
The need for greater functionality and performance in semiconductor devices has resulted in the development of larger and more complex chips. In addition, it is often desirable to include several different functions on a single chip to obtain a xe2x80x9csystem on a chip,xe2x80x9d which generally requires both an increased chip size and a more complicated manufacturing process. These factors both tend to depress manufacturing yield. It is estimated that many such complex chips, with areas greater than 400 mm2, will generally have very poor manufacturing yield (perhaps under 10%).
One method of maintaining acceptable yields is to manufacture smaller chips, and then to interconnect those chips on a single substrate or chip carrier. Besides improved manufacturing yield, another major advantage of this approach is that the individual chips may be of different sizes, perform different functions, or be fabricated by different or incompatible methods. A conventional method of joining a semiconductor device to a carrier involves the use of controlled-collapse chip connections (C4s). For example, U.S. Pat. No. 4,489,364, assigned to International Business Machines Corporation, discloses a ceramic chip carrier for supporting an array of chips by means of solder balls, such as C4s, to form a multichip module (MCM). As an example, as shown in FIG. 1, four separate chips 10 are mounted on a carrier 11; the carrier includes the wiring necessary to interconnect the chips. A C4 chip/carrier joining method typically requires an array of pads of about 100 xcexcm diameter, with the pads at approximately a 200 xcexcm pitch. Such MCMs tend to be expensive, due to their multilayered ceramic structure, and require significantly more area than the combined area of the chips. For devices which require a joining pitch below 150 xcexcm, another method must be used.
To realize the advantages offered by the system-on-a-chip (SOC) concept, it becomes necessary for all of the different chip functions to be in very close proximity and have very precise alignment with respect to each other. The alignment and interconnection should also be performed with minimal added complexity in the overall process. In the case of an SOC, the interconnections should be made on top of the chips rather than in the chip carrier substrate.
There remains a need for a process for fabricating a device having a dense arrangement of chips and a high wiring density of chip-to-chip interconnections which can be practiced with high manufacturing yield.
The present invention addresses the above-described need by providing a method for fabricating a semiconductor device including a chip, in which very fine-pitch connections are made between chips by using matching stud/via structures.
According to a first aspect of the invention, a stud is provided on a first surface of a chip (the surface closest to the active area), and a first layer is formed on a plate which is transparent to ablating radiation. The first layer includes a conducting pad on a surface of the layer opposite the plate, and generally has electrical wiring therein for device interconnection. A second layer is formed on that surface of the first layer, and a via is formed in the second layer to expose the conducting pad; the alignment substrate, the first layer and the second layer form a temporary alignment structure. The stud on the chip surface is then aligned and inserted into the via, and the chip is attached to the alignment structure. The first surface of the chip thus contacts the second layer and the stud makes electrical contact with the conducting pad (so that a stud/via connection is made). A support is then attached to the chip (or array of chips) on the backside thereof. The interface between the first layer and the transparent plate is ablated using ablating radiation (typically laser radiation) transmitted through the plate, thereby detaching the plate.
The chip (or chip array) and the alignment structure may be fully bonded by performing a lamination process. To ensure thermal conductivity from the chip to the support material, the support may be attached by forming an alloy between metal layers deposited on the backside of the chip and on the top surface of the support. Alternatively, the chip array and support may be attached by forming stud/via connections (e.g. studs on the back surfaces of the chips with vias formed in a layer deposited on the support). If the chips are of different thicknesses, the chips are planarized (typically by grinding and/or chemical-mechanical polishing) before the support is attached.
The detaching and removal of the transparent plate exposes a surface of the first layer. In order to permit interconnection with other carriers, connection pads such as C4 pads are formed on this surface.
According to a second aspect of the invention, a stud is provided on the first layer formed on the transparent plate, while a via is formed in a second layer on the first surface of the chip. The stud is aligned to the via, and the chip is attached to the alignment structure so that the first layer contacts the second layer and the stud makes electrical contact with the conducting pad.
After the stud and via are aligned, the chip and the alignment structure may be bonded by a lamination process, as noted above. The support substrate may also be attached by metallizing the chip and support and forming an alloy therebetween, or by making stud/via connections. If the chips are of different thicknesses, the chips are planarized. A backside support is then attached to the chip (or array of chips). The interface between the first layer and the transparent plate is ablated using ablating radiation transmitted through the plate, thereby detaching the plate.
According to another aspect of the invention, a semiconductor device is provided which includes a plurality of chips. A support is attached to the chips on the back surfaces thereof. A first layer is disposed on the front surfaces of the chips; this layer has a plurality of vias formed therein and conducting pads in registration with the vias. A plurality of studs, corresponding to the vias, are disposed in the vias. A second layer is attached to the first layer on a surface of the first layer opposite the front surfaces of the chips. This second layer is aligned to the first layer by the studs in the vias. The second layer includes electrical wiring connecting to the chips through the studs and the conducting pads.
The electrical wiring in the second layer makes electrical connections between the chips. The stud/via structures may be formed either with the studs in contact with the front surfaces of the chips or with the studs in contact with the second layer.
The support may be attached to the back surfaces of the chips by a metal alloy layer, or by a layer which includes stud/via structures. Electrical connection pads (such as C4 pads) may be provided on the second layer.